From 6c50eade80c176ed232ad12ae6af3c32e2addf32 Mon Sep 17 00:00:00 2001
From: Hane <inupwd@gmail.com>
Date: Mon, 17 Jul 2023 23:02:32 +0200
Subject: [PATCH] amd momento de hacerte pensar

---
 src/main.cpp | 92 +++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 80 insertions(+), 12 deletions(-)

diff --git a/src/main.cpp b/src/main.cpp
index fc694d2..67f79d9 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -28,7 +28,7 @@ Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B
 #include <iostream>
 #include "debug.h"
 
-bool checkInvariantTSC(){
+bool checkInvariantTSC(){ //Generic
 	uint64_t rdx; 
 	asm volatile (".intel_syntax noprefix\t\n" \
 				  "mov eax, 0x80000007\t\n"		\
@@ -40,9 +40,18 @@ bool checkInvariantTSC(){
 }
 
 /*
-15H	NOTES: If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
 
-EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency. If ECX is 0, the nominal core crystal clock frequency is not enumerated. "TSC frequency" = "core crystal clock frequency" * EBX/EAX. The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
+  1er comentario: https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-computation/m-p/1193432
+
+  https://community.intel.com/t5/Software-Tuning-Performance/i5-8250U-1-6-GHz-has-a-base-frequency-of-1-8-GHz/m-p/1155718/highlight/true
+ 
+15H
+NOTES: If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
+
+EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
+If ECX is 0, the nominal core crystal clock frequency is not enumerated.
+"TSC frequency" = "core crystal clock frequency" * EBX/EAX.
+The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
 
 EAX Bits 31-00: An unsigned integer which is the denominator of the TSC/"core crystal clock" ratio.
 EBX Bits 31-00: An unsigned integer which is the numerator of the TSC/"core crystal clock" ratio.
@@ -50,14 +59,67 @@ ECX Bits 31-00: An unsigned integer which is the nominal frequency of the core c
 EDX Bits 31-00: Reserved = 0.
 
  */
-void checkFrequencyTSC(uint64_t* freq){
-	if (logicore == nullptr) return NULL;
-	uint64_t raxlo,rdxho, rcx;
-    asm volatile ( ".intel_syntax noprefix\t\n"
-				   "rdtscp\t\n"
-				   "lfence\t\n": "=a" (raxlo), "=d" (rdxho), "=c" (rcx) );
+
+char** AMDMeCagoEnTusPutosMuertos () {
+	char** palabritas = (char**)malloc(sizeof(char) * 48);
+	uint64_t siguienteLetra = 0;
+	//char letrita;
+	uint64_t regs[4];//rax rbx, rcx, rdx;
+	asm volatile ( ".intel_syntax noprefix\t\n" \
+				   "mov eax, 0x80000002\t\n"	\
+				   "cpuid\t\n" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3]) );
+	int byte = 0;
+	for (int reg = 0; reg < 4; reg++, siguienteLetra++, byte = 0){
+		char* letrita = nullptr;
+		char* charifiedReg = (char*)&regs[reg];
+		for(; byte < 4; byte++){
+			letrita = (char*)malloc(sizeof(char));
+			*letrita = charifiedReg[byte];
+			*palabritas[siguienteLetra] = *letrita;
+		}
+		//uint8_t num = 0;
+		//byte = 0;
+		
+		//char* letrita = malloc(sizeof(char));
+		//letrita* = 0;
+		//letrita* |= (;
+		
+	}
+	*palabritas[siguienteLetra + 1] = '\0';
+	return palabritas;
+}
+
+int16_t checkFrequencyTSC(uint64_t* freq){
+	if (freq == nullptr) return -1;
+	uint64_t raxde;
+	asm volatile ( ".intel_syntax noprefix\t\n" \
+				   "mov eax, 0x0\t\n"	\
+				   "cpuid\t\n" : "=a" (raxde) );
+
+	if (raxde < 15) {
+		//check tsc existence??????
+		uint64_t rdxmsr;
+		asm volatile ( ".intel_syntax noprefix\t\n" \
+					   "mov eax, 0x01\t\n"			\
+					   "cpuid\t\n" : "=a" (raxde), "=d" (rdxmsr) );
+		if (!((1<<5) & rdxmsr)) return -3;
+		asm volatile ( ".intel_syntax noprefix\t\n" \
+					   "mov eax, 0x01\t\n"			\
+					   "cpuid\t\n" : "=a" (raxde), "=d" (rdxmsr) );
+		
+  
+	}
+	
+	uint64_t rbxnum, rcxhz;
+    asm volatile ( ".intel_syntax noprefix\t\n" \
+				   "mov eax, 0x15\t\n"	\
+				   "cpuid\t\n" : "=a" (raxde), "=b" (rbxnum), "=c" (rcxhz) );
 				   //"rdtscp\n" : "=a" (raxlo), "=d" (rdxho));
-	freq
+	if (rbxnum == 0 || rcxhz == 0) return -2;
+	//also 18.17.4 Invariant Time-Keepin Volume 3 Intel
+	uint64_t TSCFreq = (rcxhz * rbxnum)/raxde;
+	*freq = TSCFreq;
+	return 0;
 }
 
 //static inline
@@ -84,9 +146,15 @@ uint64_t rdtscp(uint64_t* logicore ) {
 }
 
 int main(int argc, char** argv){
+	//AMD Momento
+	char** opiniones = AMDMeCagoEnTusPutosMuertos();
+	//Cordura
+	int16_t result;
+	uint64_t tf = 0;
+	uint64_t* TSCFreq = &tf;
 	bool iTSC = checkInvariantTSC();
-	log_debugcpp(iTSC);
-	if (iTSC) {
+	result = checkFrequencyTSC(TSCFreq);
+	if (iTSC && !result) {
 		uint64_t test = rdtsc();
 		log_debugcpp(test);
 		uint64_t ayo = 0;