noosbros...

src/main.cpp

@@ -10,7 +10,7 @@ In the Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3B
 
 Does this formally imply that the TSC is always synchronized across all cores?
 
-By default the TSC is synchronized across all cores. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction. Take a look at quotes below and I hope they finally answer your question:
+By default the TSC is synchronized across all cores. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction. Take a look at quotes below and I hope they finally answer your estion:
 
 Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B & 3C): System Programming Guide Order Number: 325384-044US August 2012 Page 571 17.13 TIME-STAMP COUNTER ... Constant TSC behavior ensures that the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core changes frequency. ... Page 572 17.13.3 Time-Stamp Counter Adjustment ... Software can modify the value of the time-stamp counter (TSC) of a logical processor by using the WRMSR instruction to write to the IA32_TIME_STAMP_COUNTER MSR (address 10H). Because such a write applies only to that logical processor, software seeking to synchronize the TSC values of multiple logical processors must perform these writes on each logical processor. It may be difficult for software to do this in a way than ensures that all logical processors will have the same value for the TSC at a given point in time. The synchronization of TSC adjustment can be simplified by using the 64-bit IA32_TSC_ADJUST MSR ( address 3BH ). Like the IA32_TIME_STAMP_COUNTER MSR, the IA32_TSC_ADJUST MSR is maintained separately for each logical processor. ...
 
@@ -18,7 +18,14 @@ Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B
 
 //TSC is incremented by the base multiplier once every reference clock, so on my Xeon E5-2680 (Sandy Bridge EP) this is an increment of 27 every 10 ns
 
-//#ifdef WIN64
+#ifdef _WIN64
+    //#include <Windows.h>
+    #include <synchapi.h>
+    #define WIN32_LEAN_AND_MEAN
+#endif
+#ifdef NOMESELDELINUS
+    //hilitos y tal
+#endif
 
 #ifndef DEBUG
     #define DEBUG
@@ -59,39 +66,31 @@ ECX Bits 31-00: An unsigned integer which is the nominal frequency of the core c
 EDX Bits 31-00: Reserved = 0.
 
  */
-//Extended name on AMD systems when using 8000_002-4. Now converted to Extpagequant/vendor. Hijos de puta.
 char* AMDMeCagoEnTusPutosMuertos () {
-	char* palabritas = (char*)malloc(sizeof(char) * 48);
+	/*
-	//char* palabritas = (char*)calloc(48, sizeof(char));
+	 * Extended name on AMD systems when using 8000_002-4. 8000_0000 for Extpagequant/vendor. Hijos de puta.
+	 * Now parsing 0H for standard brand name
+	 */
+	char* palabritas = (char*)malloc(sizeof(char) * 12);
 	uint8_t siguienteLetra = 0;
-	//char letrita;
+	//uint64_t regs[4]; //rax rbx, rcx, rdx; Was used for Extended name/vendor
-	uint64_t regs[4];//rax rbx, rcx, rdx;
+	uint64_t regs[3];//rbx, rcx, rdx;
 	asm volatile ( ".intel_syntax noprefix\t\n" \
-				   "mov eax, 0x80000000\t\n"	\
+				   "mov eax, 0x0\t\n"	\
-				   "cpuid\t\n" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3]) );
+				   "cpuid\t\n" : "=b" (regs[0]), "=c" (regs[2]), "=d" (regs[1]) );
 	int byte = 0;
 	for (int reg = 0; reg < 4; reg++, byte = 0){
 		char* charifiedReg = (char*)&regs[reg];
 		for(; byte < 4; byte++, siguienteLetra++ ){ 
-			//letrita = (char*)malloc(sizeof(char));
-			//*letrita = charifiedReg[byte];
-			//*palabritas[siguienteLetra] = *letrita;
 			palabritas[siguienteLetra] = charifiedReg[byte];
 		}
-		//uint8_t num = 0;
-		//byte = 0;
-		
-		//char* letrita = malloc(sizeof(char));
-		//letrita* = 0;
-		//letrita* |= (;
-		
 	}
 	palabritas[(siguienteLetra + 1)] = '\0';
 	return palabritas;
 }
 
 //GMET on??????????? jfc wtf
-bool AMDJoder(){
+bool AMDJoderMET(){
 	uint64_t rdx;
 	asm volatile ( ".intel_syntax noprefix\t\n" \
 			   "mov eax, 0x8000000A\t\n"	\
@@ -144,21 +143,31 @@ uint64_t rdtsc() {
 }
 
 //static inline
-uint64_t rdtscp(uint64_t* logicore ) {
+uint64_t rdtscp(uint64_t* logicore = nullptr ) {
-	if (logicore == nullptr) return NULL;
 	uint64_t raxlo,rdxho, rcx;
     asm volatile ( ".intel_syntax noprefix\t\n"
 				   "rdtscp\t\n"
 				   "lfence\t\n": "=a" (raxlo), "=d" (rdxho), "=c" (rcx) );
 				   //"rdtscp\n" : "=a" (raxlo), "=d" (rdxho));
-	*logicore = rcx;
+	if (logicore == nullptr) *logicore = rcx;
 	return (rdxho << 32) + raxlo; //|
 }
 
+uint64_t estimandoFreq(){
+	uint64_t test = rdtsc();
+	Sleep(1000);
+	test = rdtsc() - test;
+	return test;
+}
+
 int main(int argc, char** argv){
 	//AMD Momento
 	char* opiniones = AMDMeCagoEnTusPutosMuertos();
-	bool w11 = AMDJoder();
+	bool w11 = AMDJoderMET();
+	for (int i = 0; i < 3; i++) {
+		uint64_t isItActually32GHz = estimandoFreq();
+		log_debugcpp("ayo we found " << isItActually32GHz << " flash knuckle");
+	}
 	//Cordura
 	int16_t result;
 	uint64_t tf = 0;