diff --git a/src/main.cpp b/src/main.cpp
index 1d31057..fc694d2 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -16,6 +16,8 @@ Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B
 
  */
 
+//TSC is incremented by the base multiplier once every reference clock, so on my Xeon E5-2680 (Sandy Bridge EP) this is an increment of 27 every 10 ns
+
 //#ifdef WIN64
 
 #ifndef DEBUG
@@ -35,7 +37,29 @@ bool checkInvariantTSC(){
 	bool iTSC = rdx & (1<<8);
 		 //"and edx, 10000000\n")
 	return iTSC;
-}	
+}
+
+/*
+15H	NOTES: If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
+
+EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency. If ECX is 0, the nominal core crystal clock frequency is not enumerated. "TSC frequency" = "core crystal clock frequency" * EBX/EAX. The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
+
+EAX Bits 31-00: An unsigned integer which is the denominator of the TSC/"core crystal clock" ratio.
+EBX Bits 31-00: An unsigned integer which is the numerator of the TSC/"core crystal clock" ratio.
+ECX Bits 31-00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.
+EDX Bits 31-00: Reserved = 0.
+
+ */
+void checkFrequencyTSC(uint64_t* freq){
+	if (logicore == nullptr) return NULL;
+	uint64_t raxlo,rdxho, rcx;
+    asm volatile ( ".intel_syntax noprefix\t\n"
+				   "rdtscp\t\n"
+				   "lfence\t\n": "=a" (raxlo), "=d" (rdxho), "=c" (rcx) );
+				   //"rdtscp\n" : "=a" (raxlo), "=d" (rdxho));
+	freq
+}
+
 //static inline
 uint64_t rdtsc() {
     uint64_t raxlo,rdxho;
@@ -49,6 +73,7 @@ uint64_t rdtsc() {
 
 //static inline
 uint64_t rdtscp(uint64_t* logicore ) {
+	if (logicore == nullptr) return NULL;
 	uint64_t raxlo,rdxho, rcx;
     asm volatile ( ".intel_syntax noprefix\t\n"
 				   "rdtscp\t\n"